Shrinking transistors has relied on thinner, higher-permittivity gate dielectrics, while treating the boundary where charge is screened on the gate side as fixed. An international team shows that this boundary can be engineered by converting the surface of the topological insulator Bi2Se3 into insulating, high-κ BiF3.
Calculations reveal a distinctive buried interface with a localised dipole, and capacitor measurements detect a series response that lowers the nominal capacitance. Despite this, MoS2 transistors with these gate stacks switch close to the thermionic limit, with negligible hysteresis and weaker drain-bias dependence than controls. QMAT's Zhipei Sun, one of the corresponding authors, and Aalto colleagues including Md Gius Uddin and Xiaoqi Cui co-authored the work with partners in South Korea, the UK, the US, Singapore and China.
The preprint has not yet been peer reviewed.
Image: QMAT